The present invention relates to data processing systems, and more particularly, the present invention relates to error control code structures for use in data processing systems.
When digital information is transferred, recorded or reproduced, in some instances errors can occur in portions of the digital information, due for example to the effects of alpha rays or other cosmic rays, to defects or noise in the transmission channel, and so on. There are known technologies that employ error detecting code or error correction code in order to detect such errors and correct any detected errors. In principle, there is no difference between error detecting codes and error correction codes, and they may be referred to collectively as error control codes. Similarly, the use of error detection and error correction may be referred to collectively as error control.
In transferring or recording digital information using error control codes, for example, m-bit error control information (redundant bits) is appended to k-bit digital information (information bits) to generate a (k+m)-bit codeword. The (k+m) bit codeword is then transmitted across a communication channel. At the transfer destination of the codeword (i.e. the receiver), error detection or error correction is performed using the redundant bits contained in the codeword. The process of generating the codeword is termed “encoding”, while the process of error detection and/or error correction based on the codeword is termed “decoding.”
With a view to further improving reliability during transmission or recording of digital information, it may be desirable to employ error control codes having high error correction/error detection capability. However, when codes with high error correction/error detection capability are used, the bit length of the redundant bits tends to be longer, and the efficiency of information transmission tends to decline.